`timescale 1 ns / 100 ps

module BCDToReverser_tb;

	reg clk;
	reg rst_n;
	reg load_flag;
	reg start_stop;
	reg mode_sel;
	reg [15:0] reset_val;
	reg [15:0] load_val;

	wire [7:0] lsb_reverser_output;
	wire [7:0] msb_reverser_output;

	BCDToReverser dut (
		clk,
		rst_n,
		load_flag,
		start_stop,
		mode_sel,
		reset_val,
		load_val,
		lsb_reverser_output,
		msb_reverser_output
	);

	initial begin
		clk = 0;
		forever #1 clk = ~clk;
	end

	initial begin
		rst_n      = 0;
		load_flag  = 0;
		start_stop = 0;
		mode_sel   = 0;
		reset_val  = 16'd0;
		load_val   = 16'd0;

		#100;
		rst_n      = 1;
		#50;
		mode_sel   = 0;
		#2;  start_stop = 1;
		#4;  start_stop = 0;

		#4000000000;
		#4000000000;
		#4000000000;
		#4000000000;

		#2;  start_stop = 1;
		#4;  start_stop = 0;

		rst_n      = 0;
		#2;  rst_n = 1;
		#2;  mode_sel = 1;
		#2;  start_stop = 1;
		#4;  start_stop = 0;

		#4000000000;
		#4000000000;
		#4000000000;

		start_stop = 0;
		#100;
		$stop;
	end

endmodule
